1. Field of the Invention
The embodiments of the invention generally relate to clock generation circuits and, more particularly, to a clock generation circuit having an improved deskewer.
2. Description of the Related Art
Clock circuits provide precise timing so that digital circuits can function properly. They do so by generating a series of high and low pulses. These high and low pulses are typically generated at a fixed frequency that is measured by the number of high and low transitions that occur per second. The transitions are used as reference for critical actions executed within digital circuits. For example, as discussed by Milton in U.S. Pat. No. 6,507,230, Jan. 14, 2003 (incorporated herein by reference and referred to hereinafter as Milton) clock signals are utilized to synchronize bus cycles of digital logic circuits. Thus, digital logic circuits initiate data operations based on clock signals and, specifically, change their output states in conjunction with the rising and/or falling edge of clock signals.
Also, as discussed in Milton, when multiple clock generators are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, a difference in delay time, referred to as skew, may occur among the clock signal inputs to the various digital logic circuits. Therefore, Milton discloses a clock generator that provides for reduced clock skews by incorporating a deskewer into each of the clock generators. However, there remains a need in the art for clock generator that provides improved timing and testability.